VHDL

VHDL (VHSIC Hardware Description Language) is an industry standard for describing, modeling, and synthesizing digital circuits and systems. Hardware descriptions written in VHDL can be used by software tools to create actual digital circuits in PLA and FPGAs.

Introduction

VHDL is a hardware design language and is unlike traditional software programming languages.

At a basic level, VHDL requires an entity and architecture construct.

An entity construct describes the functionality of a circuit and is analogous to function declaration in a C header file. An entity lists the various inputs and outputs of the underlying circuitry.

entity my_entity is
port(
  port_name_1 : in std_logic ;
  port_name_2 : out std_logic;
  port_name_3 : inout std_logic ); --do not forget the semicolon
end my_entity; -- do not forget this semicolon either

ENTITY compare8 IS PORT(
    x, y:  IN std_logic_vector(7 DOWNTO 0) ;
    res: OUT std_logic );
END compare8;

The keyword port followed by a parenthesis specifies the IO behavior of the entity. The keywords in, out, and inout specify the direction of the signal. Some signals can be vectors (ie. a bus, or a bundle). In the example above, x and y are 8 bits with 7 being the most significant.

The architecture construct describes the logic behind the entity. Each architecture construct has a name and the entity it is implemented for. The reason for the unique name is because an entity may have more than one architecture.

Signals are assigned with the {{{1}}} operator.

architecture struct OF compare8 IS
BEGIN
    res <= '1' WHEN (x = y) ELSE '0';
END struct;

Some VHDL standard libraries are required. The examples above uses std_logic which is defined in the IEEE Standard 1164 package. Standard libraries can be imported by declaring at the top of the file:

library ieee;
use ieee.std_logic_1164.all;

Glossary

synthesis: When software tools convert VHDL into actual digital circuits. Similar to how code gets compiled into a binary.

VHDL

Introduction

Glossary

See Also

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