From Leo's Notes
Last edited on 15 June 2020, at 00:49.

Most modern RAM chips come in the form of DDR (Double Data Rate) SDRAM memory.

Speed & Timings

DDR chip speed is written as DDRX-Y, where X is the DDR generation and Y the transfer rate (MT/s, millions of transfers per second). Because DDR memory triggers on both the up and down latch of the clock, the transfer rate is double the clock speed. For example, a DDR3-1600 is a DDR3 chip capable of 1600MT/s and runs at 800MHz.

Entire assembled memory modules (ie. DIMMS) speeds are written as PCX-Y, where X is the DDR generation and Y the maximum bandwidth in MB/s. Note that the last 2 digits are truncated to 0's (Eg. a PC2-4200 has a maximum bandwidth of 4266.66 MB/s).

Memory modules may have a different theoretical transfer rate than the individual DDR chips that makes up the module because these chips tend to run below the maximum clock speed. DDR memory modules transfer data on a bus that is 64 bits wide, or 8 bytes per transfer. As such, the maximum bandwidth is transfers_per_second * 8 MB/s.

Memory timings are written as: CL-tRCD-tRP-tRAS-CMD.

CL The CL number represents the CAS latency (CL, or Access Time). This value denotes how many clock cycles are required for a memory module to return data. A CL7 will require 7 clock cycles for data to be available.
tRCD The tRCD value is the RAS to CAS delay. The number of clock cycles needed to activate the line (RAS, Row Address Strobe) and column (CAS, Column Address Strobe) of the data.
tRP The tRP value is the RAS Precharge delay. The number of clock cycles required between disabling and enabling another row.
tRAS The tRAS value is the Active to Precharge delay. The number of clock cycles required before access to a different row can be initiated.
CMD The CMD value is the command rate. It is the time required between activation of the module to when the first command can be sent. This is usually omitted but is typically 1 or 2 clock cycles.

See Also