SSD: Difference between revisions
No edit summary |
|||
| Line 3: | Line 3: | ||
== Components == | == Components == | ||
=== Controller === | === Controller === | ||
The SSD controller provides an interface to the NAND flash memory and has a significant impact on the SSD performance. Other | The SSD controller provides an interface to the NAND flash memory and has a significant impact on the SSD performance. Other tasks that are dealt with by the controller are: | ||
* Bad block mapping | * Bad block mapping | ||
* Read/write cache | * Read/write cache | ||
| Line 12: | Line 12: | ||
=== Memory === | === Memory === | ||
SSDs use flash memory to retain data. Flash memory stores information in an array of memory cells constructed from floating-gate transistors | ==== Operation ==== | ||
SSDs use flash memory to retain data. Flash memory stores information in an array of memory cells constructed from floating-gate transistors (Floating-Gate MOSFET, or FGMOS). The floating-gate is a gate that is electrically isolated and can only be altered through injection or tunneling operations. | |||
The charge in the floating gate will affect how current flows through the transistor by partially canceling out the electric field from the control gate. By applying an intermediate voltage to the control gate and sensing the current through the gate, it is possible to determine the 1 bit value (for Single-Level Cell, or '''SLC''') or multiple values (2 or more bits for Multiple-level cell, or '''MLC''') stored in the cell. | |||
Floating-gates are erased using Fowler-Nordheim Tunneling. This is done by applying a high enough voltage between the source/drain/substrate and the control gate. Electrons in the floating gate will 'tunnel' through the oxide layer thereby erasing its value back to 1 (no electrons represents 1). | |||
[[File:Fntunnel.png]] | [[File:Fntunnel.png]] | ||
Inversely, floating-gates are written to using hot electron injection. | |||
[[File:Hot electron injection.png]] | [[File:Hot electron injection.png]] | ||
==== Single-, Multiple-Level Cells ==== | |||
Each floating gate holds a charge. Intuitively, a cell can store a binary bit. With a smarter controller that has a analog to digital converter (ADC), it is possible to use multiple charge states to store more bits. | |||
By using multiple charge states, there is less tolerance between charge states which leads to higher chances for errors, at the expense of allowing for higher data density. It is important for the SSD controller to handle possible errors due to MLC flash memory with error correcting codes. | |||
# SLC - Single Level, 1 bit per cell | |||
# MLC - Multiple Level, 2 bits per cell | |||
# TLC - Triple Level, 3 bits per cell | |||
# QLC - Quad Level, 4 bits per cell | |||
==== Types ==== | |||
Two common flash memories are: NOR and NAND. | Two common flash memories are: NOR and NAND. | ||
| Line 30: | Line 42: | ||
NAND flash memory is cheaper because cells can be chained in series rather than NOR where cells are in parallel. There is also less wiring required for NAND cells which increases data density. Higher densities can be achieved by stacking these NAND memory arrays on top of each other (3D-NAND) | NAND flash memory is cheaper because cells can be chained in series rather than NOR where cells are in parallel. There is also less wiring required for NAND cells which increases data density. Higher densities can be achieved by stacking these NAND memory arrays on top of each other (3D-NAND) | ||
== Host Interfaces == | |||
* Serial attached SCSI (SAS, 12.0 Gbit/s) – generally found on servers | |||
* Serial ATA (SATA, 6.0 Gbit/s) | |||
** Mini-SATA or mSATA - for laptops and ultrabooks around ~2011 | |||
* Peripheral Component Interconnect Express (PCIe, 31.5 Gbit/s at PCIe 3.0 x4) | |||
* M.2 Compatible with SATA3 and PCIE. | |||
* Fibre Channel (128 Gbit/s) – almost exclusively found on servers | |||
* USB (10 Gbit/s) | |||
* Parallel ATA (UMDA, 1064 Mbit/s) – mostly replaced by SATA | |||
* (Parallel) SCSI (> 40 Mbit/s) – generally found on servers, mostly replaced by SAS; last SCSI-based SSD was introduced in 2004 | |||
== | == Protocols == | ||
Two main protocols | |||
* AHCI - Advanced Host Controller Interface. Used by SATA based drives. | |||
* NVME - Non-Volatile Memory Express. Tailored specifically for PCIE-based drives. | |||
In terms of performance, NVME SSDs performs better with higher IOPS because of more command queues in parallel. For comparison, AHCI can process up to 32 commands with one command queue while NVME has up to 65,000 command queues with up to 65,000 commands per queue. | |||
== Reliability | == Reliability == | ||
SSDs store data in electrical charges. This will slowly leak over time without power. Old drives may start losing data after 1-2 years in storage, depending on temperature. | SSDs store data in electrical charges. This will slowly leak over time without power. Old drives may start losing data after 1-2 years in storage, depending on temperature. | ||
Revision as of 02:26, 19 August 2019
A SSD (short for solid-state drive) uses integrated circuits to store data persistently. Unlike traditional spinning hard disks, a solid-state disk has no moving parts.
Components
Controller
The SSD controller provides an interface to the NAND flash memory and has a significant impact on the SSD performance. Other tasks that are dealt with by the controller are:
- Bad block mapping
- Read/write cache
- Encryption
- Error detection / correction
- Garbage collection
- Wear leveling
Memory
Operation
SSDs use flash memory to retain data. Flash memory stores information in an array of memory cells constructed from floating-gate transistors (Floating-Gate MOSFET, or FGMOS). The floating-gate is a gate that is electrically isolated and can only be altered through injection or tunneling operations.
The charge in the floating gate will affect how current flows through the transistor by partially canceling out the electric field from the control gate. By applying an intermediate voltage to the control gate and sensing the current through the gate, it is possible to determine the 1 bit value (for Single-Level Cell, or SLC) or multiple values (2 or more bits for Multiple-level cell, or MLC) stored in the cell.
Floating-gates are erased using Fowler-Nordheim Tunneling. This is done by applying a high enough voltage between the source/drain/substrate and the control gate. Electrons in the floating gate will 'tunnel' through the oxide layer thereby erasing its value back to 1 (no electrons represents 1).
Inversely, floating-gates are written to using hot electron injection.
Single-, Multiple-Level Cells
Each floating gate holds a charge. Intuitively, a cell can store a binary bit. With a smarter controller that has a analog to digital converter (ADC), it is possible to use multiple charge states to store more bits.
By using multiple charge states, there is less tolerance between charge states which leads to higher chances for errors, at the expense of allowing for higher data density. It is important for the SSD controller to handle possible errors due to MLC flash memory with error correcting codes.
- SLC - Single Level, 1 bit per cell
- MLC - Multiple Level, 2 bits per cell
- TLC - Triple Level, 3 bits per cell
- QLC - Quad Level, 4 bits per cell
Types
Two common flash memories are: NOR and NAND.
NOR flash cells are connected in parallel and acts like a NOR gate. Reading a particular cell requires all other cells in the arrangement to be turned off so that no current flows except through the cell that is being read.
NAND flash bit cells are connected in series and acts like a NAND gate. Reading a particular bit cell requires all other bit cells in the arrangement to be turned on so that they allow current to flow freely except for the cell that is being read.
NAND flash memory is cheaper because cells can be chained in series rather than NOR where cells are in parallel. There is also less wiring required for NAND cells which increases data density. Higher densities can be achieved by stacking these NAND memory arrays on top of each other (3D-NAND)
Host Interfaces
- Serial attached SCSI (SAS, 12.0 Gbit/s) – generally found on servers
- Serial ATA (SATA, 6.0 Gbit/s)
- Mini-SATA or mSATA - for laptops and ultrabooks around ~2011
- Peripheral Component Interconnect Express (PCIe, 31.5 Gbit/s at PCIe 3.0 x4)
- M.2 Compatible with SATA3 and PCIE.
- Fibre Channel (128 Gbit/s) – almost exclusively found on servers
- USB (10 Gbit/s)
- Parallel ATA (UMDA, 1064 Mbit/s) – mostly replaced by SATA
- (Parallel) SCSI (> 40 Mbit/s) – generally found on servers, mostly replaced by SAS; last SCSI-based SSD was introduced in 2004
Protocols
Two main protocols
- AHCI - Advanced Host Controller Interface. Used by SATA based drives.
- NVME - Non-Volatile Memory Express. Tailored specifically for PCIE-based drives.
In terms of performance, NVME SSDs performs better with higher IOPS because of more command queues in parallel. For comparison, AHCI can process up to 32 commands with one command queue while NVME has up to 65,000 command queues with up to 65,000 commands per queue.
Reliability
SSDs store data in electrical charges. This will slowly leak over time without power. Old drives may start losing data after 1-2 years in storage, depending on temperature.