VHDL - Revision history

Leo: Added category

2020-06-14T23:40:45Z

Added category

← Older revision		Revision as of 23:40, 14 June 2020
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	* https://web.archive.org/web/20150118041147/https://courses.cit.cornell.edu/ee475/tutorial/VHDLTut.htm		* https://web.archive.org/web/20150118041147/https://courses.cit.cornell.edu/ee475/tutorial/VHDLTut.htm
	* http://esd.cs.ucr.edu/labs/tutorial/#gates		* http://esd.cs.ucr.edu/labs/tutorial/#gates

			{{Navbox Tinkering}}[[Category:Tinkering]]

Leo at 03:40, 1 May 2020

2020-05-01T03:40:23Z

← Older revision		Revision as of 03:40, 1 May 2020
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	* Free Range VHDL		* Free Range VHDL
	* https://web.archive.org/web/20150118041147/https://courses.cit.cornell.edu/ee475/tutorial/VHDLTut.htm		* https://web.archive.org/web/20150118041147/https://courses.cit.cornell.edu/ee475/tutorial/VHDLTut.htm
			* http://esd.cs.ucr.edu/labs/tutorial/#gates

Leo at 03:38, 1 May 2020

2020-05-01T03:38:09Z

← Older revision		Revision as of 03:38, 1 May 2020
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	port_name_3 : inout std_logic ); --do not forget the semicolon		port_name_3 : inout std_logic ); --do not forget the semicolon
	end my_entity; -- do not forget this semicolon either		end my_entity; -- do not forget this semicolon either

			ENTITY compare8 IS PORT(
			x, y: IN std_logic_vector(7 DOWNTO 0) ;
			res: OUT std_logic );
			END compare8;
	}}		}}

	The keyword port followed by a parenthesis specifies the IO behavior of the entity. The keywords {{code\|in}}, {{code\|out}}, and {{code\|inout}} specify the direction of the signal.		The keyword port followed by a parenthesis specifies the IO behavior of the entity. The keywords {{code\|in}}, {{code\|out}}, and {{code\|inout}} specify the direction of the signal. Some signals can be vectors (ie. a bus, or a bundle). In the example above, x and y are 8 bits with 7 being the most significant.

	The architecture construct describes the logic behind the entity. Each architecture construct has a name and the entity it is implemented for. The reason for the unique name is because an entity may have more than one architecture.		The architecture construct describes the logic behind the entity. Each architecture construct has a name and the entity it is implemented for. The reason for the unique name is because an entity may have more than one architecture.
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	== See Also ==		== See Also ==
	* Free Range VHDL		* Free Range VHDL
			* https://web.archive.org/web/20150118041147/https://courses.cit.cornell.edu/ee475/tutorial/VHDLTut.htm

Leo: Created page with "VHDL (VHSIC Hardware Description Language) is an industry standard for describing, modeling, and synthesizing digital circuits and systems. Hardware descriptions written in V..."

2020-05-01T03:23:47Z

Created page with "VHDL (VHSIC Hardware Description Language) is an industry standard for describing, modeling, and synthesizing digital circuits and systems. Hardware descriptions written in V..."

New page

VHDL (VHSIC Hardware Description Language) is an industry standard for describing, modeling, and synthesizing digital circuits and systems. Hardware descriptions written in VHDL can be used by software tools to create actual digital circuits in PLA and FPGAs.

== Introduction ==
VHDL is a hardware design language and is unlike traditional software programming languages.

At a basic level, VHDL requires an entity and architecture construct.

An entity construct describes the functionality of a circuit and is analogous to function declaration in a C header file. An entity lists the various inputs and outputs of the underlying circuitry.

{{highlight|lang=vhdl|code=
entity my_entity is
port(
port_name_1 : in std_logic ;
port_name_2 : out std_logic;
port_name_3 : inout std_logic ); --do not forget the semicolon
end my_entity; -- do not forget this semicolon either
}}

The keyword port followed by a parenthesis specifies the IO behavior of the entity. The keywords {{code|in}}, {{code|out}}, and {{code|inout}} specify the direction of the signal.

The architecture construct describes the logic behind the entity. Each architecture construct has a name and the entity it is implemented for. The reason for the unique name is because an entity may have more than one architecture.

Signals are assigned with the {{code|<=}} operator.

{{highlight|lang=vhdl|code=
architecture struct OF compare8 IS
BEGIN
res <= '1' WHEN (x = y) ELSE '0';
END struct;
}}

Some VHDL standard libraries are required. The examples above uses std_logic which is defined in the IEEE Standard 1164 package. Standard libraries can be imported by declaring at the top of the file:

{{highlight|lang=vhdl|code=
library ieee;
use ieee.std_logic_1164.all;
}}

== Glossary ==
; synthesis
: When software tools convert VHDL into actual digital circuits. Similar to how code gets ''compiled'' into a binary.

== See Also ==
* Free Range VHDL