SSD - Revision history

Leo at 06:00, 14 March 2022

2022-03-14T06:00:11Z

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	For the precise TBW values that a particular SSD has, refer to the SSD's data sheet. For example, a 2TB Western Digital Blue 3D NAND (WDS200T2B0A) has a TBW endurance of 500TB, while a higher end Samsung 860 PRO 512GB has a TBW endurance of 600TB, or about 5x more by capacity.		For the precise TBW values that a particular SSD has, refer to the SSD's data sheet. For example, a 2TB Western Digital Blue 3D NAND (WDS200T2B0A) has a TBW endurance of 500TB, while a higher end Samsung 860 PRO 512GB has a TBW endurance of 600TB, or about 5x more by capacity.

			See also:

			* https://semiconductor.samsung.com/resources/warranty/SAMSUNG_SSD_Limited_Warranty_English_UK.pdf - Samsung's TBW values

	====Types====		====Types====

Leo at 00:39, 15 December 2021

2021-12-15T00:39:26Z

Show changes

Leo: Text replacement - "Category:Hardware" to "{{Navbox Hardware}}Category:Hardware"

2020-06-15T00:42:39Z

Text replacement - "Category:Hardware" to "{{Navbox Hardware}}Category:Hardware"

← Older revision		Revision as of 00:42, 15 June 2020
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	[[Category:Hardware]]		{{Navbox Hardware}}[[Category:Hardware]]

Leo: /* Crypto */

2019-12-31T22:20:30Z

Crypto

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	ATA Security is the original standard for ATA (IBM PC/AT Attachment) storage devices. It defines the ''security feature set'' which allows for locking and unlocking with a password. SEDs (ab)used the ATA security password for encryption.		ATA Security is the original standard for ATA (IBM PC/AT Attachment) storage devices. It defines the ''security feature set'' which allows for locking and unlocking with a password. SEDs (ab)used the ATA security password for encryption.

	TCG Opal is the newer specification for SEDs. The protocol is layered on top of ATA or NVMe and mandates AES-128 or AES-256. Multiple passwords can be defined. A storage device can be divided into multiple ''locking ranges'' that can be locked or unlocked independently with each encrypted with a different DEK (Media Encryption Key in Opal terminology). A global range is defined to cover all sectors. ~~EMultiple~~ passwords can be assigned permissions to unlock particular ranges.		TCG (Trusted Computing Group) Opal is the newer specification for SEDs. The protocol is layered on top of ATA or NVMe and mandates AES-128 or AES-256. Multiple passwords can be defined. A storage device can be divided into multiple ''locking ranges'' that can be locked or unlocked independently with each encrypted with a different DEK (Media Encryption Key in Opal terminology). A global range is defined to cover all sectors. Multiple passwords can be assigned permissions to unlock particular ranges.

	== Reliability ==		== Reliability ==

Leo at 19:57, 31 December 2019

2019-12-31T19:57:11Z

← Older revision		Revision as of 19:57, 31 December 2019
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	Two main protocols		Two main protocols
	* '''AHCI''' - Advanced Host Controller Interface. Used by SATA based drives.		* '''AHCI''' - Advanced Host Controller Interface. Used by SATA based drives.
	* '''~~NVME~~''' - Non-Volatile Memory Express. Tailored specifically for PCIE-based drives.		* '''NVMe''' - Non-Volatile Memory Express. Tailored specifically for PCIE-based drives.

	In terms of performance, NVME SSDs performs better with higher IOPS because of more command queues in parallel. For comparison, AHCI can process up to 32 commands with one command queue while NVME has up to 65,000 command queues with up to 65,000 commands per queue.		In terms of performance, NVME SSDs performs better with higher IOPS because of more command queues in parallel. For comparison, AHCI can process up to 32 commands with one command queue while NVME has up to 65,000 command queues with up to 65,000 commands per queue.

			== Crypto ==
			SSDs with encryption support (self-encrypting drives, or '''SED'''s for short) contains a dedicated AES co-processor to offload encryption and to avoid negatively impacting data throughput. Encryption uses the disk encryption key ('''DEK''') which can be password protected. The password for a DEK can also be changed without needing to re-encrypting the entire contents of the drive. With encryption enabled, data can be protected by protecting the DEK or wiped by erasing the DEK.

			ATA Security is the original standard for ATA (IBM PC/AT Attachment) storage devices. It defines the ''security feature set'' which allows for locking and unlocking with a password. SEDs (ab)used the ATA security password for encryption.

			TCG Opal is the newer specification for SEDs. The protocol is layered on top of ATA or NVMe and mandates AES-128 or AES-256. Multiple passwords can be defined. A storage device can be divided into multiple ''locking ranges'' that can be locked or unlocked independently with each encrypted with a different DEK (Media Encryption Key in Opal terminology). A global range is defined to cover all sectors. EMultiple passwords can be assigned permissions to unlock particular ranges.

	== Reliability ==		== Reliability ==

Leo: hardware category

2019-09-02T01:41:47Z

hardware category

← Older revision		Revision as of 01:41, 2 September 2019
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	fsutil behavior set disabledeletenotify 0		fsutil behavior set disabledeletenotify 0
	}}		}}


			[[Category:Hardware]]

Leo at 22:01, 31 August 2019

2019-08-31T22:01:17Z

@@ Line 62: / Line 62: @@
 NOR flash cells are connected in parallel and acts like a NOR gate. Reading a particular cell requires all other cells in the arrangement to be turned off so that no current flows except through the cell that is being read.
-NAND flash bit cells are connected in series and acts like a NAND gate. Reading a particular bit cell requires all other bit cells in the arrangement to be turned on so that they allow current to flow freely except for the cell that is being read.
+NAND flash bit cells are connected in series and acts like a NAND gate. Reading a particular bit cell requires all other bit cells in the arrangement to be turned on so that they allow current to flow freely except for the cell that is being read.  Writing a particular bit requires all other bits in the arrangement to be rewritten.
 NAND flash memory is cheaper because cells can be chained in series rather than NOR where cells are in parallel. There is also less wiring required for NAND cells which increases data density. Higher densities can be achieved by stacking these NAND memory arrays on top of each other (3D-NAND)
@@ Line 99: / Line 99: @@
 == Reliability ==
-SSDs store data as electrical charges in floating gates. This charge will slowly leak over time without power. Old drives may start losing data after 1-2 years in storage, depending on temperature and P/E cycles.
+== Garbage Collection & TRIM ==

Leo: /* Single-, Multiple-Level Cells */

2019-08-31T21:25:01Z

Single-, Multiple-Level Cells

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	Inversely, floating-gates are written to using hot electron injection.		Inversely, floating-gates are written to using hot electron injection.

	==== Single-, ~~Multiple~~-Level Cells ====		==== Single-, Multi-Level Cells ====
	Each floating gate holds a charge. Intuitively, a cell can store a binary bit. With a smarter controller that is able to differentiate multiple charge states, higher data density can be achieved by storing additional bits in each cell. This comes at the expense of less tolerance between charge states resulting in a higher chance for errors as well as higher latencies for erasing and programming. Errors are handled by the controller using error correcting codes.		Each floating gate holds a charge. Intuitively, a cell can store a binary bit. With a smarter controller that is able to differentiate multiple charge states, higher data density can be achieved by storing additional bits in each cell. This comes at the expense of less tolerance between charge states resulting in a higher chance for errors as well as higher latencies for erasing and programming. Errors are handled by the controller using error correcting codes.

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	\|-		\|-
	! Program / Erase		! Program / Erase
	\| 100,000 \|\| 10,000 \|\| 5,000 \|\| 2,000		\| 100,000 \|\| 10,000 \|\| 3,000 \|\| 1,000
	\|}		\|}
			[[File:QLC Density.jpg\|550px\|frameless\|right\|SLC, MLC, TLC, QLC Densities]]
	Each cell has a limited number of writes before the floating gate breaks down. In the context of whole SSDs, the number of writes before the floating gates begin to break down is represented as '''Terabytes Written''' or '''TBW'''. Terrabytes Written is the total number of data that can be written to a SSD before it is expected to fail.		Each cell has a limited number of writes before the floating gate breaks down. In the context of whole SSDs, the number of writes before the floating gates begin to break down is represented as '''Terabytes Written''' or '''TBW'''. Terrabytes Written is the total number of data that can be written to a SSD before it is expected to fail.

	Because each additional bit stored per cell will store double the amount of data stored, each additional bit will also double the expected writes per cell and thus reduce a cell's life by half. Therefore, a QLC SSD with 4 bits per cell will likely have half the expected writes of a TLC, a quarter of the writes of a MLC SSD, or an 8th of the writes of a SLC before failure.		Because each additional bit stored per cell will store double the amount of data stored, each additional bit will also double the expected writes per cell and thus reduce a cell's life by half. Therefore, a QLC SSD with 4 bits per cell will likely have half the expected writes of a TLC, a quarter of the writes of a MLC SSD, or an 8th of the writes of a SLC before failure.

			Additionally, higher level cells have slower read/write times. It is typical for multi-level SSDs to come with a small amount of SLC storage for caching writes.

	==== Types ====		==== Types ====

Leo at 21:15, 31 August 2019

2019-08-31T21:15:13Z

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	=== Memory ===		=== Memory ===
	==== Operation ====		==== Operation ====
			[[File:Fntunnel.png\|thumb\|350px\|right]]
	SSDs use flash memory to retain data. Flash memory stores information in an array of memory cells constructed from floating-gate transistors (Floating-Gate MOSFET, or FGMOS). The floating-gate is a gate that is electrically isolated and can only be altered through injection or tunneling operations.		SSDs use flash memory to retain data. Flash memory stores information in an array of memory cells constructed from floating-gate transistors (Floating-Gate MOSFET, or FGMOS). The floating-gate is a gate that is electrically isolated and can only be altered through injection or tunneling operations.

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	Floating-gates are erased using Fowler-Nordheim Tunneling. This is done by applying a high enough voltage between the source/drain/substrate and the control gate. Electrons in the floating gate will 'tunnel' through the oxide layer thereby erasing its value back to 1 (no electrons represents 1).		Floating-gates are erased using Fowler-Nordheim Tunneling. This is done by applying a high enough voltage between the source/drain/substrate and the control gate. Electrons in the floating gate will 'tunnel' through the oxide layer thereby erasing its value back to 1 (no electrons represents 1).
	~~[[File:Fntunnel.png\|150px\|frame\|right]]~~

			[[File:Hot electron injection.png\|350px\|thumb\|right]]
	Inversely, floating-gates are written to using hot electron injection.		Inversely, floating-gates are written to using hot electron injection.
	~~[[File:Hot electron injection.png\|150px\|frame\|right]]~~

	==== Single-, Multiple-Level Cells ====		==== Single-, Multiple-Level Cells ====

Leo at 21:11, 31 August 2019

2019-08-31T21:11:52Z

← Older revision		Revision as of 21:11, 31 August 2019
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	SSDs use flash memory to retain data. Flash memory stores information in an array of memory cells constructed from floating-gate transistors (Floating-Gate MOSFET, or FGMOS). The floating-gate is a gate that is electrically isolated and can only be altered through injection or tunneling operations.		SSDs use flash memory to retain data. Flash memory stores information in an array of memory cells constructed from floating-gate transistors (Floating-Gate MOSFET, or FGMOS). The floating-gate is a gate that is electrically isolated and can only be altered through injection or tunneling operations.

	The charge in the floating gate will affect how current flows through the transistor by partially canceling out the electric field from the control gate. By applying an intermediate voltage to the control gate and sensing the current through the gate, it is possible to determine the ~~1 bit~~ value ~~(for Single-Level Cell, or '''SLC''') or multiple values (2 or more bits for Multiple-level cell, or '''MLC''')~~ stored in the cell.		The charge in the floating gate will affect how current flows through the transistor by partially canceling out the electric field from the control gate. By applying an intermediate voltage to the control gate and sensing the current through the gate, it is possible to sense and determine the value stored in the cell.

	Floating-gates are erased using Fowler-Nordheim Tunneling. This is done by applying a high enough voltage between the source/drain/substrate and the control gate. Electrons in the floating gate will 'tunnel' through the oxide layer thereby erasing its value back to 1 (no electrons represents 1).		Floating-gates are erased using Fowler-Nordheim Tunneling. This is done by applying a high enough voltage between the source/drain/substrate and the control gate. Electrons in the floating gate will 'tunnel' through the oxide layer thereby erasing its value back to 1 (no electrons represents 1).
	[[File:Fntunnel.png]]		[[File:Fntunnel.png\|150px\|frame\|right]]

	Inversely, floating-gates are written to using hot electron injection.		Inversely, floating-gates are written to using hot electron injection.
	[[File:Hot electron injection.png]]		[[File:Hot electron injection.png\|150px\|frame\|right]]

	==== Single-, Multiple-Level Cells ====		==== Single-, Multiple-Level Cells ====
	Each floating gate holds a charge. Intuitively, a cell can store a binary bit. With a smarter controller that ~~has a analog to digital converter (ADC), it~~ is ~~possible~~ to ~~use~~ multiple charge states ~~to store more~~ bits.		Each floating gate holds a charge. Intuitively, a cell can store a binary bit. With a smarter controller that is able to differentiate multiple charge states, higher data density can be achieved by storing additional bits in each cell. This comes at the expense of less tolerance between charge states resulting in a higher chance for errors as well as higher latencies for erasing and programming. Errors are handled by the controller using error correcting codes.

	~~By using multiple charge states~~, ~~there is less tolerance between charge states which leads to higher chances for errors~~, at the ~~expense~~ of ~~allowing for higher data density~~. It is ~~important for~~ the SSD ~~controller~~ to ~~handle possible errors due to MLC flash memory with error correcting codes~~.		{\| class="wikitable center"
			\|-
			! !! SLC !! MLC !! TLC !! QLC
			\|-
			! Name \|\| Single Level \|\| Multi Level \|\| Triple Level \|\| Quad Level
			\|-
			! Bits per Cell
			\| 1 \|\| 2 \|\| 3 \|\| 4
			\|-
			! Charge States
			\| 2 \|\| 4 \|\| 8 \|\| 16
			\|-
			! Read latency (us)
			\| 25 \|\| 50 \|\| 100 \|\| ??
			\|-
			! Write latency (us)
			\| 250 \|\| 900 \|\| 1500 \|\| ??
			\|-
			! Erase latency (us)
			\| 1500 \|\| 3000 \|\| 5000 \|\| ??
			\|-
			! Program / Erase
			\| 100,000 \|\| 10,000 \|\| 5,000 \|\| 2,000
			\|}

			Each cell has a limited number of writes before the floating gate breaks down. In the context of whole SSDs, the number of writes before the floating gates begin to break down is represented as '''Terabytes Written''' or '''TBW'''. Terrabytes Written is the total number of data that can be written to a SSD before it is expected to fail.

	~~# SLC - Single Level, 1~~ bit per cell		Because each additional bit stored per cell will store double the amount of data stored, each additional bit will also double the expected writes per cell and thus reduce a cell's life by half. Therefore, a QLC SSD with 4 bits per cell will likely have half the expected writes of a TLC, a quarter of the writes of a MLC SSD, or an 8th of the writes of a SLC before failure.
	~~# MLC - Multiple Level~~, ~~2 bits~~ per cell
	~~# TLC - Triple Level~~, ~~3 bits per cell~~
	# QLC ~~- Quad Level,~~ 4 bits per cell

	==== Types ====		==== Types ====
	~~Two~~ common flash memories ~~are:~~ NOR ~~and~~ NAND.		While there are two common types of non-volatile flash memories (NAND and NOR), nearly all SSDs today use NAND flash.

	NOR flash cells are connected in parallel and acts like a NOR gate. Reading a particular cell requires all other cells in the arrangement to be turned off so that no current flows except through the cell that is being read.		NOR flash cells are connected in parallel and acts like a NOR gate. Reading a particular cell requires all other cells in the arrangement to be turned off so that no current flows except through the cell that is being read.
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	== Protocols ==		== Protocols ==
	Two main protocols		Two main protocols
	* AHCI - Advanced Host Controller Interface. Used by SATA based drives.		* '''AHCI''' - Advanced Host Controller Interface. Used by SATA based drives.
	* NVME - Non-Volatile Memory Express. Tailored specifically for PCIE-based drives.		* '''NVME''' - Non-Volatile Memory Express. Tailored specifically for PCIE-based drives.

	In terms of performance, NVME SSDs performs better with higher IOPS because of more command queues in parallel. For comparison, AHCI can process up to 32 commands with one command queue while NVME has up to 65,000 command queues with up to 65,000 commands per queue.		In terms of performance, NVME SSDs performs better with higher IOPS because of more command queues in parallel. For comparison, AHCI can process up to 32 commands with one command queue while NVME has up to 65,000 command queues with up to 65,000 commands per queue.
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	== Reliability ==		== Reliability ==

	SSDs store data in electrical charges. This will slowly leak over time without power. Old drives may start losing data after 1-2 years in storage, depending on temperature.		SSDs store data as electrical charges in floating gates. This charge will slowly leak over time without power. Old drives may start losing data after 1-2 years in storage, depending on temperature and P/E cycles.