RAM - Revision history

Leo: Text replacement - "Category:Hardware" to "{{Navbox Hardware}}Category:Hardware"

2020-06-15T00:49:08Z

Text replacement - "Category:Hardware" to "{{Navbox Hardware}}Category:Hardware"

← Older revision		Revision as of 00:49, 15 June 2020
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	* https://www.hardwaresecrets.com/understanding-ram-timings/		* https://www.hardwaresecrets.com/understanding-ram-timings/

	[[Category:Hardware]]		{{Navbox Hardware}}[[Category:Hardware]]

Leo: Added category

2020-06-14T23:52:18Z

Added category

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	* https://en.wikipedia.org/wiki/DDR3_SDRAM#Modules		* https://en.wikipedia.org/wiki/DDR3_SDRAM#Modules
	* https://www.hardwaresecrets.com/understanding-ram-timings/		* https://www.hardwaresecrets.com/understanding-ram-timings/

			[[Category:Hardware]]

Leo: /* Speed & Timings */

2019-12-04T22:40:09Z

Speed & Timings

← Older revision		Revision as of 22:40, 4 December 2019
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	Entire assembled memory modules (ie. DIMMS) speeds are written as {{code\|PCX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the maximum bandwidth in MB/s. Note that the last 2 digits are truncated to 0's (Eg. a PC2-4200 has a maximum bandwidth of 4266.66 MB/s).		Entire assembled memory modules (ie. DIMMS) speeds are written as {{code\|PCX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the maximum bandwidth in MB/s. Note that the last 2 digits are truncated to 0's (Eg. a PC2-4200 has a maximum bandwidth of 4266.66 MB/s).

	Memory modules may have a different theoretical transfer rate than the individual DDR chips that makes up the module because these chips tend to run below the maximum clock speed. DDR memory modules transfer data on a bus that is 64 bits wide, or 8 bytes per transfer. As such, the maximum bandwidth is {{code\|~~clock_speed~~ * 8}} MB/s.		Memory modules may have a different theoretical transfer rate than the individual DDR chips that makes up the module because these chips tend to run below the maximum clock speed. DDR memory modules transfer data on a bus that is 64 bits wide, or 8 bytes per transfer. As such, the maximum bandwidth is {{code\|transfers_per_second * 8}} MB/s.

	Memory timings are written as: {{code\|CL-tRCD-tRP-tRAS-CMD}}.		Memory timings are written as: {{code\|CL-tRCD-tRP-tRAS-CMD}}.

Leo at 22:04, 4 December 2019

2019-12-04T22:04:52Z

← Older revision		Revision as of 22:04, 4 December 2019
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	== Speed & Timings ==		== Speed & Timings ==
	DDR ~~chips are classified~~ as {{code\|DDRX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the ~~maximum clock speed~~. Because DDR memory triggers on both the up and down latch, the ~~actual bus~~ clock ~~speed driving~~ the ~~module~~ is ~~half~~ the ~~labeled~~ clock speed. For example, a {{code\|DDR3-1600}} is a DDR3 chip ~~running~~ at 800MHz.		DDR chip speed is written as {{code\|DDRX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the transfer rate (MT/s, millions of transfers per second). Because DDR memory triggers on both the up and down latch of the clock, the transfer rate is double the clock speed. For example, a {{code\|DDR3-1600}} is a DDR3 chip capable of 1600MT/s and runs at 800MHz.

	Entire memory modules are ~~classified~~ as {{code\|PCX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the maximum ~~transfer rate~~ in MB/s.		Entire assembled memory modules (ie. DIMMS) speeds are written as {{code\|PCX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the maximum bandwidth in MB/s. Note that the last 2 digits are truncated to 0's (Eg. a PC2-4200 has a maximum bandwidth of 4266.66 MB/s).

	Memory modules may have a different theoretical transfer rate than the individual DDR chips that makes up the module because these chips tend to run below the maximum clock speed. ~~DIMMs send and receive~~ 64 bits ~~of data~~, so the maximum ~~transfer rate~~ is {{code\|clock_speed * ~~64bits~~}} ~~Mbits~~/s.		Memory modules may have a different theoretical transfer rate than the individual DDR chips that makes up the module because these chips tend to run below the maximum clock speed. DDR memory modules transfer data on a bus that is 64 bits wide, or 8 bytes per transfer. As such, the maximum bandwidth is {{code\|clock_speed * 8}} MB/s.

	Memory timings are written as: {{code\|CL-tRCD-tRP-tRAS-CMD}}.		Memory timings are written as: {{code\|CL-tRCD-tRP-tRAS-CMD}}.

Leo at 20:42, 4 December 2019

2019-12-04T20:42:49Z

← Older revision		Revision as of 20:42, 4 December 2019
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			Most modern RAM chips come in the form of DDR (Double Data Rate) SDRAM memory.

	== Speed & Timings ==		== Speed & Timings ==
	DDR chips are classified as {{code\|DDRX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the maximum clock speed. For example, a {{code\|DDR3-1600}} is a DDR3 chip running at ~~1600MHz~~.		DDR chips are classified as {{code\|DDRX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the maximum clock speed. Because DDR memory triggers on both the up and down latch, the actual bus clock speed driving the module is half the labeled clock speed. For example, a {{code\|DDR3-1600}} is a DDR3 chip running at 800MHz.

	Entire memory modules are classified as {{code\|PCX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the maximum transfer rate in MB/s.		Entire memory modules are classified as {{code\|PCX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the maximum transfer rate in MB/s.

	Memory modules may have a different theoretical transfer rate than the individual DDR chips that makes up the module because these chips tend to run below the maximum clock speed.		Memory modules may have a different theoretical transfer rate than the individual DDR chips that makes up the module because these chips tend to run below the maximum clock speed. DIMMs send and receive 64 bits of data, so the maximum transfer rate is {{code\|clock_speed * 64bits}} Mbits/s.

			Memory timings are written as: {{code\|CL-tRCD-tRP-tRAS-CMD}}.
	Memory timings are written as: {{code\|CL-tRCD-tRP-tRAS-CMD}}:
	{\| class="wikitable"		{\| class="wikitable"
	! CL		! CL
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	\|-		\|-
	! tRCD		! tRCD
	\| The tRCD ~~number~~ is the RAS to CAS delay. The ~~time~~ needed to activate the line (RAS, Row Address Strobe) and column (CAS, Column Address Strobe) of the data.		\| The tRCD value is the RAS to CAS delay. The number of clock cycles needed to activate the line (RAS, Row Address Strobe) and column (CAS, Column Address Strobe) of the data.
	\|-		\|-
	! tRP		! tRP
	\| The tRP ~~number~~ is the RAS Precharge delay. ~~It is the time~~ required between disabling and enabling another ~~data line~~.		\| The tRP value is the RAS Precharge delay. The number of clock cycles required between disabling and enabling another row.
	\|-		\|-
	! tRAS		! tRAS
	\| The tRAS ~~number~~ is the Active to Precharge delay. ~~It is the amount~~ of ~~time~~ required before ~~the next~~ access can be initiated.		\| The tRAS value is the Active to Precharge delay. The number of clock cycles required before access to a different row can be initiated.
	\|-		\|-
	! CMD		! CMD
	\| The CMD ~~number~~ is the command rate. It is the time required between activation of the module to when the first command can be sent.		\| The CMD value is the command rate. It is the time required between activation of the module to when the first command can be sent. This is usually omitted but is typically 1 or 2 clock cycles.
	\|}		\|}


	== See Also ==		== See Also ==
			* https://en.wikipedia.org/wiki/DDR3_SDRAM#Modules
	* https://www.hardwaresecrets.com/understanding-ram-timings/		* https://www.hardwaresecrets.com/understanding-ram-timings/

Leo: Created page with " == Speed & Timings == DDR chips are classified as {{code|DDRX-Y}}, where {{code|X}} is the DDR generation and {{code|Y}} the maximum clock speed. For example, a {{code|DDR3-..."

2019-12-04T20:26:17Z

Created page with " == Speed & Timings == DDR chips are classified as {{code|DDRX-Y}}, where {{code|X}} is the DDR generation and {{code|Y}} the maximum clock speed. For example, a {{code|DDR3-..."

New page

== Speed & Timings ==
DDR chips are classified as {{code|DDRX-Y}}, where {{code|X}} is the DDR generation and {{code|Y}} the maximum clock speed. For example, a {{code|DDR3-1600}} is a DDR3 chip running at 1600MHz.

Entire memory modules are classified as {{code|PCX-Y}}, where {{code|X}} is the DDR generation and {{code|Y}} the maximum transfer rate in MB/s.

Memory modules may have a different theoretical transfer rate than the individual DDR chips that makes up the module because these chips tend to run below the maximum clock speed.

Memory timings are written as: {{code|CL-tRCD-tRP-tRAS-CMD}}:
{| class="wikitable"
! CL
| The CL number represents the CAS latency (CL, or Access Time). This value denotes how many clock cycles are required for a memory module to return data. A CL7 will require 7 clock cycles for data to be available.
|-
! tRCD
| The tRCD number is the RAS to CAS delay. The time needed to activate the line (RAS, Row Address Strobe) and column (CAS, Column Address Strobe) of the data.
|-
! tRP
| The tRP number is the RAS Precharge delay. It is the time required between disabling and enabling another data line.
|-
! tRAS
| The tRAS number is the Active to Precharge delay. It is the amount of time required before the next access can be initiated.
|-
! CMD
| The CMD number is the command rate. It is the time required between activation of the module to when the first command can be sent.
|}

== See Also ==
* https://www.hardwaresecrets.com/understanding-ram-timings/

← Older revision		Revision as of 22:40, 4 December 2019
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	Entire assembled memory modules (ie. DIMMS) speeds are written as {{code\|PCX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the maximum bandwidth in MB/s. Note that the last 2 digits are truncated to 0's (Eg. a PC2-4200 has a maximum bandwidth of 4266.66 MB/s).		Entire assembled memory modules (ie. DIMMS) speeds are written as {{code\|PCX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the maximum bandwidth in MB/s. Note that the last 2 digits are truncated to 0's (Eg. a PC2-4200 has a maximum bandwidth of 4266.66 MB/s).

	Memory modules may have a different theoretical transfer rate than the individual DDR chips that makes up the module because these chips tend to run below the maximum clock speed. DDR memory modules transfer data on a bus that is 64 bits wide, or 8 bytes per transfer. As such, the maximum bandwidth is {{code\|~~clock_speed~~ * 8}} MB/s.		Memory modules may have a different theoretical transfer rate than the individual DDR chips that makes up the module because these chips tend to run below the maximum clock speed. DDR memory modules transfer data on a bus that is 64 bits wide, or 8 bytes per transfer. As such, the maximum bandwidth is {{code\|transfers_per_second * 8}} MB/s.

	Memory timings are written as: {{code\|CL-tRCD-tRP-tRAS-CMD}}.		Memory timings are written as: {{code\|CL-tRCD-tRP-tRAS-CMD}}.

← Older revision		Revision as of 22:04, 4 December 2019
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	== Speed & Timings ==		== Speed & Timings ==
	DDR ~~chips are classified~~ as {{code\|DDRX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the ~~maximum clock speed~~. Because DDR memory triggers on both the up and down latch, the ~~actual bus~~ clock ~~speed driving~~ the ~~module~~ is ~~half~~ the ~~labeled~~ clock speed. For example, a {{code\|DDR3-1600}} is a DDR3 chip ~~running~~ at 800MHz.		DDR chip speed is written as {{code\|DDRX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the transfer rate (MT/s, millions of transfers per second). Because DDR memory triggers on both the up and down latch of the clock, the transfer rate is double the clock speed. For example, a {{code\|DDR3-1600}} is a DDR3 chip capable of 1600MT/s and runs at 800MHz.

	Entire memory modules are ~~classified~~ as {{code\|PCX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the maximum ~~transfer rate~~ in MB/s.		Entire assembled memory modules (ie. DIMMS) speeds are written as {{code\|PCX-Y}}, where {{code\|X}} is the DDR generation and {{code\|Y}} the maximum bandwidth in MB/s. Note that the last 2 digits are truncated to 0's (Eg. a PC2-4200 has a maximum bandwidth of 4266.66 MB/s).

	Memory modules may have a different theoretical transfer rate than the individual DDR chips that makes up the module because these chips tend to run below the maximum clock speed. ~~DIMMs send and receive~~ 64 bits ~~of data~~, so the maximum ~~transfer rate~~ is {{code\|clock_speed * ~~64bits~~}} ~~Mbits~~/s.		Memory modules may have a different theoretical transfer rate than the individual DDR chips that makes up the module because these chips tend to run below the maximum clock speed. DDR memory modules transfer data on a bus that is 64 bits wide, or 8 bytes per transfer. As such, the maximum bandwidth is {{code\|clock_speed * 8}} MB/s.

	Memory timings are written as: {{code\|CL-tRCD-tRP-tRAS-CMD}}.		Memory timings are written as: {{code\|CL-tRCD-tRP-tRAS-CMD}}.